1. Field of the Invention
The invention relates to a circuit arrangement for converting a data signal having a constant bit rate and code words of different length into an output signal consisting of code words of constant length but with a variable bit rate while using a buffer memory, in which arrangement a first encoder is provided which recognizes the code words of the data signal and converts them into code words of equal length and in which these code words are written in the buffer memory, read out from this memory by a second encoder and converted into code words of the output signal.
2. Prior Art
A circuit arrangement of this type is described in German Patent Application No. P 35 10.901.7 It is used, for example for decoding received video data and the associated control words which are transmitted as a code word sequence consisting of code words of variable length in order to maintain the bit rate of the transmission signal as small as possible. FIG. 1 shows a basic circuit diagram of the above-mentioned circuit arrangement.
A received data signal DS consisting of video data and control words and the bit clock T of the data signal are applied to a first encoder U1 via input terminals. The bit rate of the data signal DS is 2 Mbit/s. The encoder U1 which is in the form of a fast microprocessor in accordance with the above-mentioned German Patent Application recognizes the words of unequal length in the received data signal DS and converts them into 10-bit code words. These 10-bit code words are written in a buffer memory PS by means of a write clock TS. The specification for converting the data signal into the 10-bit code words is chosen to be such that the 10-bit code are to be changed to a slight extent in order to obtain the code words of the data signal in the ultimately required form. The video data and control words are not separated at this point.
The code words of the data signal acquire their ultimate form by means of a second encoder U2 which reads the 10-bit code words by means of a read clock TL from the buffer memory PS and converts them into code words of the output signal.
The code words of the output signals are present in a parallel form at the output terminals of the second encoder U2. The video data and control words are separated in such a way that the decoded video data DVD can be derived from eight output terminals, whilst the decoded control words SS are present at the remaining output terminals. This separation mode results from the conversion table in the second encoder U2 formed as an EPROM.
As stated above, the first encoder U1 in the above-mentioned Patent Application is in the form of a microprocessor whose function is essentially determined by the programs stored in its associated program memory.